]> git.the-white-hart.net Git - vhdl/commit
Separate CYC for flash and ram in mem controller
authorrs <>
Sun, 29 Jun 2025 22:20:26 +0000 (17:20 -0500)
committerrs <>
Sun, 29 Jun 2025 22:20:26 +0000 (17:20 -0500)
commit33d725036fe1ad7a91e55e45d8a81a7894570e90
tree77c88e7127d70105f506f3a1f3bec9037ef79cc8
parent305d9ec7dcbb1883671d78b258a49fda550e1b17
Separate CYC for flash and ram in mem controller
libraries/nexys2/mem_wb8_0.vhd
libraries/nexys2/tests/test_nexys2_mem_wb8_0.vhd
libraries/nexys2/tests/test_sim_mem_wb8_0.vhd
libraries/utility/wb_mapper_a8d8.vhd [new file with mode: 0644]