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(parent: 78f890c) | patch

author	rs <>
	Wed, 12 Nov 2025 00:41:25 +0000 (18:41 -0600)
committer	rs <>
	Wed, 12 Nov 2025 00:41:25 +0000 (18:41 -0600)
commit	12a67493af78c0b351875355e4ab8e3a19458a68
tree	95af2b4d090bc7266c3dff5660fbe2d2a4913b09	tree \| snapshot
parent	78f890c2667fa7c239aca4bb762a192697d93729	commit \| diff

Use Gray counters in clock domain crossing FIFO

libraries/utility/fifo_xclk.vhd		diff \| blob \| history
libraries/utility/gray_counter.vhd	[new file with mode: 0644]	blob
libraries/utility/tests/test_graycounter.vhd	[new file with mode: 0644]	blob

All of my VHDL libraries and projects